In the fabrication of integrated circuits (ICs), it is often necessary to polish a side of a part such as a thin flat wafer of a semiconductor material. In general, a semiconductor wafer can be polished to provide a planarized surface to remove topography, surface defects such as a crystal lattice damage, scratches, roughness, or embedded particles such as dirt or dust. This polishing process is often referred to as mechanical planarization or chemical mechanical planarization (CMP) and is utilized to improve the quality and reliability of semiconductor devices. The (CMP) process is usually performed during the formation of various devices and integrated circuits (ICs) on the wafer.
In general, the chemical mechanical planarization (CMP) process involves holding a thin flat wafer of semiconductor material against a rotating wetted polishing surface under a controlled downward pressure. A polishing slurry such as a solution of alumina or silica may be utilized as the abrasive medium. A rotating polishing head or wafer carrier is typically utilized to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft wetted pad material such as blown polyurethane.
Such apparatus for polishing thin flat semiconductor wafers are well known in the art. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh, for instance, disclose such apparatus.
FIGS. 1-2 illustrate the effect of the chemical mechanical planarization (CMP) process on a semiconductor wafer. As shown in FIG. 1, a semiconductor wafer 10 includes a substrate 12 on which a plurality of IC devices 14 have been formed. The wafer substrate 12 is typically formed of a single crystal silicon material. The IC devices 14 are typically formed by patterning regions and layers on the substrate. A chemical mechanical planarization (CMP) process may be utilized, for instance, to remove and planarize a portion of a layer such as an oxide coating 16.
As an example, and as shown in FIG. 2, it may be necessary to remove the oxide coating 16 to a planar end point such as to the level of the IC devices 14 to form insulating spacers between the IC devices 14. This can be accomplished by a chemical mechanical planarization (CMP) process. Alternately it may be necessary to remove some feature or structure formed on the substrate 12 to an end point of or to the surface of the substrate 12. Other semiconductor manufacturing processes such as polishing, roughening or thinning the wafer may also involve a chemical mechanical planarization (CMP) process.
A particular problem encountered in the chemical mechanical planarization (CMP) process is known in the art as the "loading effect." A schematic of the loading effect is illustrated in FIG. 3 and 3A. As an example, it may be necessary to remove repetitive structures 20 to an endpoint such as to the surface of a substrate 12 or a different film layer formed on the substrate 12 using chemical mechanical planarization (CMP). During the chemical mechanical planarization (CMP) process the wafer 10 is pressed against a polishing pad 18 on the polishing platen of the chemical mechanical planarization (CMP) apparatus. Since these polishing pads 18 are typically formed of a relatively soft material, such as blown polyurethane, the polishing pad 18 may deform, as shown in FIG. 3, into the area between the structures 20 to be removed. As such, the surface of the substrate 12 may be contacted by the polishing pad 18. As the structures 20 are removed by the planarization process the surface of the substrate 12 is also removed by contact with the deformed polishing pad 18. As shown in FIG. 3A, this may cause an irregular or wavy surface 22 to be formed on the substrate 12. In general, this phenomena occurs on the micro level and has an adverse affect on the IC circuits formed on the wafer 10, especially in high density applications.
Another example of the loading affect is shown in FIGS. 4 and 4A. A wafer 10 may include a plurality of transistors 22 formed on the substrate. A protective or insulating layer of a dielectric material such as borophosphorus silicate glass (BPSG) 23 may be deposited over the transistors 22. An initial conformal deposition of the (BPSG) layer 23 may produce an irregular surface with peaks directly above the transistors 22 and valleys between the transistors. As before, the polishing pad 18 may deform to accommodate the irregular surface of the (BPSG) 23 layer. The resultant polished surface may appear on the micro level as wavy or irregular as shown in FIG. 4A.
The loading effect may function in other situations to remove the sides and base of features present on the surface of a wafer during chemical mechanical planarization (CMP). In addition, the loading effect may occur locally or globally across the surface of the wafer. In addition, this problem may be compounded by the velocity differential between the outer peripheral portions and the interior portions of the rotating semiconductor wafer. The faster moving peripheral portions of the semiconductor wafer may, for instance, experience a relatively larger rate of material removal than the relatively slower moving interior portions.
In view of the foregoing, there is a need in semiconductor manufacture for a chemical mechanical planarization (CMP) process that overcomes the loading effect. Accordingly, it is an object of the present invention to provide a (CMP) process in which the loading effect is eliminated and micro-scratches are removed from the wafer.